[PATCH 85/85] [Backport to 15] Handle OpVectorShuffle with differing vector sizes (#2391) (#2412)
The SPIR-V to LLVM conversion would bail out when encountering an
`OpVectorShuffle` whose vector operands differ in size. SPIR-V
allows differing vector sizes, but LLVM's `shufflevector` does not.
Remove the assert and insert an additional `shufflevector` to align
the vector operands when needed.
bwlodarcz [Fri, 13 Oct 2023 10:33:06 +0000 (12:33 +0200)]
[PATCH 84/85] Add support for ISubBorrow SPIRV instruction (#2168)
This commit implements bidirectional translation of the llvm.usub.with.overflow and the ISubBorrow intrinsic.
Intrinsic llvm.usub.with.overflow returns struct which second element have a type of i1.
The llvm type i1 is, in llvm-spirv, directly translated to BoolType.
SPIRV specification requires that the composite which returns from ISubBorrow needs to have both elements of the same type.
In result, current implementation is not compliant and should be considered temporary.
Gbp-Pq: Name 0084-Add-support-for-ISubBorrow-SPIRV-instruction-2168.patch
bwlodarcz [Thu, 12 Oct 2023 15:13:50 +0000 (17:13 +0200)]
[PATCH 83/85] Add support for IAddCarry SPIRV instruction (#2167)
This commit implements bidirectional translation of the llvm.uadd.with.overflow and the IAddCarry intrinsic.
Intrinsic llvm.uadd.with.overflow returns struct which second element have a type of i1.
The llvm type i1 is, in llvm-spirv, directly translated to BoolType.
SPIRV specification requires that the composite which returns from IAddCarry needs to have both elements of the same type.
In result, current implementation is not compliant and should be considered temporary.
Gbp-Pq: Name 0083-Add-support-for-IAddCarry-SPIRV-instruction-2167.patch
[PATCH 80/85] [Backport to 15] Fix allowed types for OpConstantNull (#2361)
The SPIR-V Specification allows `OpConstantNull` types to be scalar or
vector booleans, integers, or floats. Update an assert for this and
add a SPIR-V -> LLVM IR test.
Wenju He [Fri, 2 Feb 2024 17:31:27 +0000 (01:31 +0800)]
[PATCH 79/79] [Backport to 15][SPV -> SPV-IR] Fix image builtin mangling of unsigned type (#2273) (#2338)
Return type of image read and Texel type of image write builtins may be unsigned. Before this PR, the builtin names in SPIR-V Friendly IR were always mangled with signed type.
[PATCH 78/79] [Backport to 15] add initial f16 type support for atomicrmw in llvm-spirv translator (#2210)
This PR aims to add f16 type support for atomicrmw in llvm-spirv translator, with the reference to the extension documented in [1].
There are two concerns related to the subject:
SPIRVAtomicFAddEXTInst::getRequiredExtension() should return a list of required extension to support the requirement to list both SPV_EXT_shader_atomic_float16_add and SPV_EXT_shader_atomic_float_add extensions in the module (see "Extension Name" section of the ref [1]). However, the return type is std::optional<ExtensionID> and returning a vector would need a bigger rework.
Including SPV_EXT_shader_atomic_float16_add into --spirv-ext argument of llvm-spirv doesn't result in producing the correspondent capability (AtomicFloat16AddEXT) and extension in a SPIRV output.
$ llvm-spirv AtomicFAddEXT.ll.tmp.bc --spirv-ext=+SPV_EXT_shader_atomic_float_add,+SPV_EXT_shader_atomic_float16_add -o AtomicFAddEXT.ll.tmp.spv
$ llvm-spirv -to-text AtomicFAddEXT.ll.tmp.spv -o /dev/stdout
...
2 Capability AtomicFloat32AddEXT
2 Capability AtomicFloat64AddEXT
9 Extension "SPV_EXT_shader_atomic_float_add"
...
This prevents extending the test case of AtomicFAddEXT.ll in EXT/SPV_EXT_shader_atomic_float.
LU-JOHN [Wed, 31 Jan 2024 13:08:38 +0000 (07:08 -0600)]
[PATCH 75/79] Preserve DIExpression in DIGlobalVariableExpression (#2324)
Ensure that SPIR-V that uses a DebugGlobalVariable's Variable field to hold an Expression
can be reverse translated. A Variable field can be used to hold an Expression in order to
preserve a DIExpression in a DIGlobalVariableExpression in LLVM IR.
Signed-off-by: Lu, John <john.lu@intel.com>
Gbp-Pq: Name 0075-Preserve-DIExpression-in-DIGlobalVariableExpression-.patch
* Bump SPIRV-Headers to 1c6bb2743599e6eb6f37b2969acc0aef812e32e3
* replace internal SPV_INTEL_long_composites ext with the published SPV_INTEL_long_composites
* don't rename extension for now
Gbp-Pq: Name 0074-Backport-to-15-Update-LongConstantCompositeINTEL-to-.patch
%0 = load <6 x i32>, ptr addrspace(1) @__spirv_BuiltInGlobalInvocationId, align 32
%1 = extractelement <6 x i32> %0, i64 0
Note the global type and load type are different. Change the handling of vector loads from vector globals to reconstruct the global vector type and then bitcast to the load type.
Thanks to @jcranmer-intel for helping me find the simplest solution.
Co-authored-by: Nick Sarnie <sarnex@users.noreply.github.com>
Gbp-Pq: Name 0073-Backport-to-15-Fix-SPIR-V-global-to-function-replace.patch
Non-constant @llvm.memset calls are presently lowered by generating synthetic
functions with the mangled name of memset. However, the reader tries to use this
name to generate the intrinsic call again. This causes verification issues if
the SPIRVWriter and SPIRVReader do not agree on whether or not to use opaque
pointers. This change uses the actual type of the function (which will take into
account whether or not it is in opaque pointer mode) to generate the LLVM
intrinsic name, fixing the mismatch issues.
Co-authored-by: Joshua Cranmer <joshua.cranmer@intel.com>
Gbp-Pq: Name 0070-Backport-to-15-OpaquePointers-Handle-llvm.memset-int.patch
I made the following changes that are not in the original changes:
Use llvm::Optional instead of std::optional
Port tests to not use opaque pointers and related flags
Fix patch fail due to missing unrelated function in this branch
Signed-off-by: Sarnie, Nick <nick.sarnie@intel.com>
Gbp-Pq: Name 0069-Backport-to-15-Backport-spirv-preserve-auxdata-chang.patch
[PATCH 66/79] [Backport to 15] [OpaquePointers] Adjust builtin variable tracking to support i8 geps (#2061)
The existing logic for the replacement of builtin variables with calls to
functions relies on relatively brittle tracking that is broken when opaque
pointers is turned on, and will be even more thoroughly broken if/when typed
geps are replaced with i8 geps or ptradd. This patch replaces that logic with a
less brittle variant that is able to handle any sequence of bitcast, gep, or
addrspacecast instructions between the global variable and the ultimate load
instruction.
It still will error out if the variable is used in too insane of a fashion (say,
trying to load an i32 out of the i64, or a misaligned vector type).
Co-authored-by: Joshua Cranmer <joshua.cranmer@intel.com>
Gbp-Pq: Name 0066-Backport-to-15-OpaquePointers-Adjust-builtin-variabl.patch
[PATCH 61/79] [DebugInfo] Adjust TypeInheritance for NonSemantic spec (#2039)
It does not have Child parameter comparing to OpenCL specification.
https://github.com/KhronosGroup/SPIRV-Registry/blob/main/nonsemantic/NonSemantic.Shader.DebugInfo.100.asciidoc#DebugTypeInheritance
Gbp-Pq: Name 0061-DebugInfo-Adjust-TypeInheritance-for-NonSemantic-spe.patch
LU-JOHN [Fri, 9 Jun 2023 12:05:17 +0000 (07:05 -0500)]
[PATCH 60/79] Implement DebugLine and DebugNoLine (#2012)
Implement DebugLine/DebugNoLine for NonSemantic.Shader.DebugInfo.100 and NonSemantic.Shader.DebugInfo.200.
Updated test/DebugInfo/NonSemantic/Shader200/DebugInfoStringType.ll to test these changes.
Gbp-Pq: Name 0060-Implement-DebugLine-and-DebugNoLine-2012.patch
[PATCH 57/79] [DebugInfo] Add Flags operand for DebugTypeBasic for NonSemantic spec (#2034)
Flags operand is not optional, fill it with DebugInfoNone value (see #1965
for clarifications why it could not be generated by clang or by LLVM
environment).
Gbp-Pq: Name 0057-DebugInfo-Add-Flags-operand-for-DebugTypeBasic-for-N.patch
[PATCH 52/79] [DebugInfo] Translate checksum info inside DebugSource instruction (#1996)
It's done in scope of NonSemantic.Shader.200.DebugInfo spec to have a
proper solution for translation of checksum info (instead of the W/A
done for OpenCL DebugInfo spec in #936)
Gbp-Pq: Name 0052-DebugInfo-Translate-checksum-info-inside-DebugSource.patch
[PATCH 50/79] [DebugInfo] Support translation of DebugSourceContinued (#1993)
Max length of SPIRV instruction is 65535 words by specification.
DebugSourceContinued helps to overcome the limitation and specify full source code text by continuing the string from the previous DebugSource(Continued)instruction.
Dmitry Sidorov [Wed, 15 Feb 2023 18:49:45 +0000 (19:49 +0100)]
[PATCH 49/79] [Backport to 15] Split JointMatrixMadINTEL instruction into 4 (#1833)
JointMatrixMadINTEL will stand for signed/signed Matrix type
JointMatrixSUMadINTEL will stand for signed/signed Matrix type
JointMatrixUSMadINTEL will stand for unsigned/signed Matrix type
JointMatrixUUMadINTEL will stand for unsigned/unsigned Matrix type
Spec update:
intel/llvm#8175
Signed-off-by: Dmitry Sidorov dmitry.sidorov@intel.com
Gbp-Pq: Name 0049-Backport-to-15-Split-JointMatrixMadINTEL-instruction.patch
[PATCH 43/79] [DebugInfo] Fix translation of Target Function operand (#1982)
Before reading Target function name operand of `DebugFunction` we need
to make sure it's the translation of appropriate debug extension.
Otherwise, we can get in a situation, where we do have 11 operands, but
the last one is not a `String` with name, but the `DebugFunctionDeclaration`.
Gbp-Pq: Name 0043-DebugInfo-Fix-translation-of-Target-Function-operand.patch
[PATCH 42/79] [DebugInfo] Translate inline namespace debug info (#1978)
In NonSemantic.Shader.DebugInfo.200 DebugLexicalBlock has Inline
namespace parameter, which specifies if C/C++ namespace is inline or not.
It allows us to save `exportSymbols` field of `DINamespace` metadata.
[PATCH 39/79] [DebugInfo] Add Flag parameter to DebugTypeBasic (#1965)
It can only be FlagUnknownPhysicalLayout. There is no way we can
generate it LLVM environment and get use of it, hence the patch just
ignores it if it come from another SPIR-V generator.
In general, there are following possible debug flags for DIBasicType:
BigEndian, LittleEndian and Artificial. There is not way that clang will
ever generate them, but that can be produced by manually writing
assembly and transforming it to LLVM IR. While it can be potential
improvement for the future - I don't see it useful to add to the spec
and implementation right now.
Signed-off-by: Sidorov, Dmitry <dmitry.sidorov@intel.com>
Gbp-Pq: Name 0039-DebugInfo-Add-Flag-parameter-to-DebugTypeBasic-1965.patch
[PATCH 37/79] [NFC] Use typed pointers for null function pointers debug info (#1969)
`PointerType::get(Context` will return typeless/opaque pointer. While it
is OK for KHR translator since it's being built on top of LLVM trunk,
where opaque pointers are enabled by default - it won't work for
intel/llvm, where their generation is disabled.
Upstream of https://github.com/intel/llvm/pull/9118
Signed-off-by: Sidorov, Dmitry <dmitry.sidorov@intel.com>
Gbp-Pq: Name 0037-NFC-Use-typed-pointers-for-null-function-pointers-de.patch
[PATCH 35/79] [Backport to 15][DebugInfo] Support translation of DebugFunctionDefinition instruction (#1961)
DebugFunction does not have an Function Id operand in NonSemantic.Shader debug info specification. It's been replaced by the whole new DebugFunctionDefinition instruction to avoid forward references.
This instruction must appear in the entry basic block of an OpFunction.
[PATCH 34/79] [Backport to 15][DebugInfo] Support multiple CompileUnits (#1950)
It's possible for LLVM IR module to contain multiple CU in case if this module is a result
of llvm-link between two modules compiled for different languages and or compiled with
different options.
This patch introduces handling of such modules.
std::unordered_map<SPIRVId, std::unique_ptr> BuilderMap was introduced
to SPIR-V consumption part and
std::unordered_map<const DICompileUnit *, SPIRVExtInst *> SPIRVCUMap was introduced
to SPIR-V generation part to preserve Scope relations between DI metadata in SPIR-V and vice versa.
Note, that DIBuilder has a single CU field and this class is not trivially copiable.
Signed-off-by: Sidorov, Dmitry <dmitry.sidorov@intel.com>
Gbp-Pq: Name 0034-Backport-to-15-DebugInfo-Support-multiple-CompileUni.patch
It's mapped on new Encoding value for DebugBasicType in NonSemantic.Shader.DebugInfo.200 spec.
If another DebugInfo instruction set is specified - it's mapped to DW_TAG_unspecified_type
Spec:
KhronosGroup/SPIRV-Registry#186
Signed-off-by: Sidorov, Dmitry <dmitry.sidorov@intel.com>
Gbp-Pq: Name 0032-DebugInfo-Add-DW_ATE_complex_float-translation-1946.patch
Mateusz Chudyk [Thu, 4 May 2023 11:32:55 +0000 (13:32 +0200)]
[PATCH 30/79] [Backport to 15] Preserve invalid SPIRV source lang literal in module metadata (#1951) (#1980)
Some SPIR-V producers generate invalid source language value (invalid =
other than the enum values defined in spv::SourceLanguage). While in
many cases this is rightly translated to DW_LANG_OpenCL, the original
source language value should be preserved in LLVM module metadata for
later use by LLVM IR consumers.
Co-authored-by: Michal Paszkowski <michal@paszkowski.org>
Gbp-Pq: Name 0030-Backport-to-15-Preserve-invalid-SPIRV-source-lang-li.patch
[PATCH 28/79] [Backport to 15][DebugInfo] Align Instruction names to the specification (#1896)
This patch fixes the discovered typos in Debug Instruction names, so we
can generate spec-conformant SPIR-V module.
https://registry.khronos.org/SPIR-V/specs/unified1/DebugInfo.html
Gbp-Pq: Name 0028-Backport-to-15-DebugInfo-Align-Instruction-names-to-.patch
Dmitry Sidorov [Tue, 21 Mar 2023 22:20:39 +0000 (23:20 +0100)]
[PATCH 25/79] [Backport to 15][DebugInfo] Start adopting debug info instructions for NonSemantic set (#1887)
List of changes:
All Literal parameters of instructions in OpenCL.DebugInfo.100
are OpConstants in NonSemantic.Shader.DebugInfo.100 and
NonSemantic.Shader.DebugInfo.200;
SPV_KHR_non_semantic_info is being implicitly added for nonsemantic
debug info;
Gbp-Pq: Name 0025-Backport-to-15-DebugInfo-Start-adopting-debug-info-i.patch
[PATCH 24/79] [Backport to 15][DebugInfo] Support translation of DIModule (#1878)
This entity represents a module in the programming language, for example a Fortran module.
Spec:
KhronosGroup/SPIRV-Registry#186
The implementation is the same as for SPV_INTEL_debug_module extension. Spec for extension:
https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_debug_module.asciidoc
Gbp-Pq: Name 0024-Backport-to-15-DebugInfo-Support-translation-of-DIMo.patch
Dmitry Sidorov [Wed, 8 Mar 2023 18:22:53 +0000 (19:22 +0100)]
[PATCH 22/79] [Backport to 15][DebugInfo] Add DebugTypeArrayDynamic translation (#1871)
This instruction describes a dynamic array, mostly for Fortran 90.
Unlike DebugTypeArray it has Data Location, Associated, Allocated
and Rank parameters. If the appropriate metadata parameters
appear in LLVM IR in DW_TAG_array_type metadata, then such
debug type becomes treated as dynamic array by the translator
(of course if the appropriate extended instruction set is enabled).
Dmitry Sidorov [Wed, 1 Mar 2023 18:23:49 +0000 (19:23 +0100)]
[PATCH 21/79] [Backport to 15][DebugInfo] Add an option for NonSemantic.Shader.DebugInfo.100 (#1855)
Under this option this extended instruction set will be implemented
Spec:
https://github.com/KhronosGroup/SPIRV-Registry/blob/main/nonsemantic/NonSemantic.Shader.DebugInfo.100.asciidoc
TODO: to rename NonSemantic.Kernel.DebugInfo.100 to
NonSemantic.Shader.DebugInfo.200 when the name is stable
Signed-off-by: Sidorov, Dmitry <dmitry.sidorov@intel.com>
Gbp-Pq: Name 0021-Backport-to-15-DebugInfo-Add-an-option-for-NonSemant.patch
[PATCH 20/79] [Backport to 15][DebugInfo] Add new Source Languages table used in DebugCompilationUnit (#1854)
This extended source language table is used by DebugCompilationUnit instruction when the extension is enabled. It enables support for more languages than exists in a core specification.
Spec: KhronosGroup/SPIRV-Registry#186
Enabling of Fortran language also allowed to fix FortranArray test that was originally XFAIL-ed in 9e234d9.
Gbp-Pq: Name 0020-Backport-to-15-DebugInfo-Add-new-Source-Languages-ta.patch
[PATCH 18/79] [Backport to 15] Initial support NonSemantic.Kernel.DebugInfo.100 (#1846)
This patch implements the initial support for the new debug specification NonSemantic.Kernel.DebugInfo.100.
It also introduces support for the new debug instruction DISubrange.
Spec: KhronosGroup/SPIRV-Registry#186
Gbp-Pq: Name 0018-Backport-to-15-Initial-support-NonSemantic.Kernel.De.patch
Dmitry Sidorov [Fri, 31 Mar 2023 11:40:26 +0000 (13:40 +0200)]
[PATCH 17/79] Update spirv-as invocations (#1933)
After SPIRV-Tools commit 2e0f4b52 ("tools: refactorize tools flags
parsing. (#5111)", 2023-02-27), spirv-as needs to be told explicitly
when reading from stdin.
Co-authored-by: Sven van Haastregt <sven.vanhaastregt@arm.com>
Gbp-Pq: Name 0017-Update-spirv-as-invocations-1933.patch
Dmitry Sidorov [Tue, 8 Nov 2022 09:40:39 +0000 (10:40 +0100)]
[PATCH 13/79] [Backport to 15] Translate readnone attribute as function parameter attribute (#1697)
Community restricted readnone, readonly and writeonly attributes
to be only function parameter attributes. This patch aligns
the translator with llvm.org.
It also fixes a bug, when readnone attribute is being mapped
to NoWrite SPIR-V function parameter attribute.
This change continues #1749.
We are removing SPV_INTEL_non_constant_addrspace_printf extension in
favor of SPV_EXT_relaxed_printf_string_address_space, which are
basically the same.
Signed-off-by: Maksimova, Viktoria <viktoria.maksimova@intel.com>
Gbp-Pq: Name 0012-Deprecate-SPV_INTEL_non_constant_addrspace_printf-ex.patch
* [Backport to 15] Relax OpenCL extended instruction restrictions (#1724)
When VectorAnyINTEL capability is enabled, OpenCL extended instructions
are able to work on vector types with any number of components greater
then or equal to 2.
* [Backport to 15] Translate LLVM intrinsics into native_* OpenCL instructions (#1729)
When an intrinsic function is called with `afn` flag, it's allowed to
substitute an approximate calculations. So the translator can emit
native versions of OpenCL extended instructions.
Co-authored-by: Victor Mustya <victor.mustya@intel.com>
Gbp-Pq: Name 0010-Backport-to-15-Relax-OpenCL-extended-instruction-res.patch
Stanley Gambarin [Fri, 11 Nov 2022 10:31:34 +0000 (02:31 -0800)]
[PATCH 08/79] [Backport to 15] Implement SPV_INTEL_tensor_float32_conversion extension (#1656) (#1700)
This extension adds conversion instruction from float to tensor float (TF32)
data format. TF32 uses 1 bit for a sign, 8 bits for an exponent and 10 bits
for a fraction. This extension doesn’t introduce TF32 type in SPIR-V, instead
instruction below uses 32-bit float type to represent TF32 value.
Spec: https://github.com/intel/llvm/pull/6990
Co-authored-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
Gbp-Pq: Name 0008-Backport-to-15-Implement-SPV_INTEL_tensor_float32_co.patch
Dmitry Sidorov [Tue, 8 Nov 2022 20:32:27 +0000 (21:32 +0100)]
[PATCH 07/79] [Backport to 15] Translate llvm.loop.unroll.full metadata (#1673)
It can be generated via #pragma clang unroll(full) pragma.
llvm.loop.unroll.full means attempt to do full unroll of the
loop and disable the unrolling if the trip count is not known
at compile time.
Unroll mask to which it was previously mapped doesn't much the
description.
The way the patch represents it in SPIR-V is:
Unroll mask + PartialCount mask with '1' parameter
This patch also removes some overtesting for unroll metadata.
This backports: https://github.com/KhronosGroup/SPIRV-LLVM-Translator/pull/1664
Signed-off-by: Sidorov, Dmitry <dmitry.sidorov@intel.com>
Gbp-Pq: Name 0007-Backport-to-15-Translate-llvm.loop.unroll.full-metad.patch
[PATCH 06/79] [Backport to 15] Add SPV_INTEL_masked_gather_scatter extension (#1580) (#1695)
This extension allows TypeVector to have a Physical Pointer Type
Component Type and introduces gather/scatter instructions.
It will be useful for explicitly vectorized kernels.
Changed the integer dot translation to use the correct function names
(i.e. dot_4x8packed or dot_acc_sat_4x8packed) to translate them into
proper OpCodes. Additionally removed unused variables from visitCallDot
Gbp-Pq: Name 0001-Integer-dot-product-4x8-packed-translation-1654.patch
* Skip upstream testsuite on big-endian architectures (> 60% of the tests
are failing anyway but ignored) due to excessive disk space usage
(> 40 GB). (Closes: #1065395)
* Update from llvm_release_150 branch (v15.0.0-85-gda050541).
* Disable two commits causing test failures.
Wenju He [Fri, 2 Feb 2024 17:31:27 +0000 (01:31 +0800)]
[PATCH 79/79] [Backport to 15][SPV -> SPV-IR] Fix image builtin mangling of unsigned type (#2273) (#2338)
Return type of image read and Texel type of image write builtins may be unsigned. Before this PR, the builtin names in SPIR-V Friendly IR were always mangled with signed type.
[PATCH 78/79] [Backport to 15] add initial f16 type support for atomicrmw in llvm-spirv translator (#2210)
This PR aims to add f16 type support for atomicrmw in llvm-spirv translator, with the reference to the extension documented in [1].
There are two concerns related to the subject:
SPIRVAtomicFAddEXTInst::getRequiredExtension() should return a list of required extension to support the requirement to list both SPV_EXT_shader_atomic_float16_add and SPV_EXT_shader_atomic_float_add extensions in the module (see "Extension Name" section of the ref [1]). However, the return type is std::optional<ExtensionID> and returning a vector would need a bigger rework.
Including SPV_EXT_shader_atomic_float16_add into --spirv-ext argument of llvm-spirv doesn't result in producing the correspondent capability (AtomicFloat16AddEXT) and extension in a SPIRV output.
$ llvm-spirv AtomicFAddEXT.ll.tmp.bc --spirv-ext=+SPV_EXT_shader_atomic_float_add,+SPV_EXT_shader_atomic_float16_add -o AtomicFAddEXT.ll.tmp.spv
$ llvm-spirv -to-text AtomicFAddEXT.ll.tmp.spv -o /dev/stdout
...
2 Capability AtomicFloat32AddEXT
2 Capability AtomicFloat64AddEXT
9 Extension "SPV_EXT_shader_atomic_float_add"
...
This prevents extending the test case of AtomicFAddEXT.ll in EXT/SPV_EXT_shader_atomic_float.
projects / spirv-llvm-translator-15.git / log